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cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B psoc ? programmable system-on-chip? cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-67345 rev. *a revised may 13, 2011 features powerful harvard-architecture processor ? m8c processor speeds up to 24 mhz ? low power at high speed ? operating voltage: 2.4 v to 5.25 v ? operating voltages down to 1. 0 v using on-chip switch mode pump (smp) ? industrial temperature range: ?40 c to +85 c advanced peripherals (psoc ? blocks) ? four analog ty pe e psoc blocks provide: ? two comparators with digital-to-analog converter (dac) references ? single or dual 10-bit 28 channel analog-to-digital converters (adc) ? four digital psoc blocks provide: ? 8- to 32-bit timers, counters , and pulse width modulators (pwms) ? cyclical redundancy check (crc) and pseudo random sequence (prs) modules ? full-duplex universal asynchro nous receiver transmitter (uart), serial peripheral interface (spi) master or slave ? connectable to all general purpose i/o (gpio) pins ? complex peripherals by combining blocks flexible on-chip memory ? 8 kb flash program storage 50,000 erase/write cycles ? 512 bytes static random a ccess memory (sram) data storage ? in-system serial programming (issp) ? partial flash updates ? flexible protection modes ? eeprom emulation in flash complete development tools ? free development software (psoc designer?) ? full-featured, in-circuit em ulator (ice) and programmer ? full-speed emulation ? complex breakpoint structure ? 128-kb trace memory precision, programmable clocking ? internal 2.5% 24- / 48-mhz main oscillator ? internal oscillator for watchdog and sleep programmable pin configurations ? 25-ma sink, 10-ma source on all gpios ? pull-up, pull-down, high z, strong, or open-drain drive modes on all gpios ? up to eight analog inputs on gpios ? configurable interrupt on all gpios smartsense? auto-tuning user module: ? smartsense auto-tuning is easy to use and provides robust noise immunity. ? smartsense tunes your capsen se system autom atically at power up and monitors the system in real time to maintain optimum performance. ? smartsense significantly reduces design cycle time by eliminating the tuning process from prototype to mass production. ? smartsense allows maximum production flexibility by compensating for variations caused by using multiple manufacturing sites and vendors. versatile analog mux ? common internal analog bus ? simultaneous connection of i/o combinations ? capacitive sensing application capability additional system resources ? i 2 c master, slave, and multi-master to 400 khz ? watchdog and sleep timers ? user-configurable low-voltage detection (lvd) ? integrated supervisory circuit ? on-chip precision voltage reference logic block diagram [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 2 of 47 contents features............................................................................. 1 logic block diagram........................................................ 1 contents ............................................................................ 2 psoc functional overview.............................................. 3 the psoc core ........................................................... 3 the digital system ...................................................... 3 the analog system ..................................................... 4 additional system resources . .................................... 4 psoc device characteristics .. .................................... 5 getting started.................................................................. 5 application notes ........................................................ 5 development kits ........................................................ 5 training ....................................................................... 5 cypros consultants .................................................... 5 solutions library.......................................................... 5 technical support ....................................................... 5 development tools .......................................................... 6 psoc designer software subsyst ems............. ........... 6 designing with psoc designer ....................................... 7 select user modules ................................................... 7 configure user modules.......... .................................... 7 organize and connect ............... .............. .............. ..... 7 generate, verify, and debug....................................... 7 smartsense................................................................. 7 pin information ................................................................. 8 16-pin part pinout ....................................................... 8 20-pin part pinout ....................................................... 9 28-pin part pinout ..................................................... 10 32-pin part pinout ..................................................... 11 56-pin part pinout ..................................................... 13 register reference......................................................... 15 register conventions ................................................ 15 register mapping tables ......... ............... .............. .... 15 electrical specifications ................................................ 18 absolute maximum ra tings....................................... 18 operating temperature ............................................. 19 dc electrical characteristics..................................... 19 ac electrical characteristics ..................................... 25 packaging information................................................... 33 thermal impedances................................................. 36 solder reflow peak temperat ure ............................. 36 development tool selection ...... .............. .............. ....... 37 software .................................................................... 37 development kits ...................................................... 37 evaluation tools........................................................ 37 device programmers................ ................................. 38 accessories (emulation and programming) .............. 38 ordering information...................................................... 39 ordering code definitions ...... ................................... 40 acronyms ........................................................................ 41 reference documents.................................................... 41 document conventions ................................................. 42 units of measure ....................................................... 42 numeric conventions ............... ................................. 42 glossary .......................................................................... 42 document history page ................................................. 47 .......................................................................................... 47 sales, solutions, and legal information ...................... 47 worldwide sales and design supp ort............. .......... 47 products .................................................................... 47 psoc solutions ......................................................... 47 [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 3 of 47 psoc functional overview the psoc family consists of many devices with on-chip controllers. these devices are designed to replace multiple traditional mcu-based system components with one low-cost single-chip programmable component. a psoc device includes configurable blocks of analog and digital logic, and programmable interconnect. this architecture makes it possible for you to create customized peripheral configurations, to match the requirements of each individual application. additionally, a fast central processing unit (cpu), flash program memory, sram data memory, and configurable i/o are included in a range of convenient pinouts. the psoc architecture, shown in figure 1 , consists of four main areas: the core, the system re sources, the digital system, and the analog system. configurable global bus resources allow combining all of the device reso urces into a complete custom system. each cy8c21x34 b psoc device includes four digital blocks and four analog blocks. depending on the psoc package, up to 28 gpios are also included. the gpios provide access to the global digital and analog interconnects. the psoc core the psoc core is a powerful engine that supports a rich instruction set. it encompasses sram for data storage, an interrupt controller, sleep and watchdog timers, and internal main oscillator (imo) and internal low speed oscillator (ilo). the cpu core, called the m8c, is a powerf ul processor with speeds up to 24 mhz. the m8c is a four-million instructions per second (mips) 8-bit harvard-architecture microprocessor. system resources provide these additional capabilities: digital clocks for increased flexibility i 2 c functionality to implement an i 2 c master and slave an internal voltage reference, multi-master, that provides an absolute value of 1.3 v to a number of psoc subsystems a smp that generates normal op erating voltages from a single battery cell various system resets supported by the m8c the digital system consists of an array of digital psoc blocks that may be configured into any number of digital peripherals. the digital blocks are connected to the gpios through a series of global buses. these buses can route any signal to any pin, freeing designs from the constr aints of a fixed peripheral controller. the analog system co nsists of four analog psoc blocks, supporting comparators, and analog-to-digital conversion up to 10 bits of precision. the digital system the digital system consists of four digital psoc blocks. each block is an 8-bit resource that is used alone or combined with other blocks to form 8-, 16-, 24- , and 32-bit peripherals, which are called user modules. digital peripheral configurations include: pwms (8- to 32-bit) pwms with dead band (8- to 32-bit) counters (8- to 32-bit) timers (8- to 32-bit) uart 8- with selectable parity serial peripheral interface (spi) master and slave i 2 c slave and multi-master crc/generator (8-bit) irda prs generators (8-bit to 32-bit) the digital blocks are connected to any gpio through a series of global buses that can route any signal to any pin. the buses also allow for signal multiplexing and for performing logic operations. this configurability frees your designs from the constraints of a fixed peripheral controller. digital blocks are provided in rows of four, where the number of blocks varies by psoc device family. this allows the optimum choice of system resources for your application. family resources are shown in table 1 on page 5 . figure 1. digital system block diagram digital system to system bus d i g i t a l c l o c k s f r o m c o r e digital psoc block array to analog system 8 row input configuration row output configuration 8 8 8 row 0 dbb00 dbb01 dcb02 dcb03 4 4 gie[7:0] gio[7:0] goe[7:0] goo[7:0] global digital interconnect port 3 port 2 port 1 port 0 [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 4 of 47 the analog system the analog system consists of four configurable blocks that allow for the creation of complex analog signal flows. analog peripherals are very flexible and can be customized to support specific application requirements. some of the common psoc analog functions for this device (most available as user modules) are: adcs (single or dual, with 8-bit or 10-bit resolution) pin-to-pin comparator single-ended comparators (up to two) with absolute (1.3 v) reference or 8-bit dac reference 1.3-v reference (as a system resource) in most psoc devices, analog blocks are provided in columns of three, which includes one continuous time (ct) and two switched capacitor (sc) blocks. the cy8c 21x34b devices provide limited functionality type e analog blocks. each co lumn contains one ct type e block and one sc type e block. refer to the psoc technical reference manual for detailed information on the cy8c21x34b?s type e analog blocks. figure 2. analog system block diagram the analog multiplexer system the analog mux bus can connect to every gpio pin. pins may be connected to the bus individual ly or in any combination. the bus also connects to the analog system for analysis with comparators and analog-to-digital converters. an additional 8:1 analog input multiplexer provides a second path to bring port 0 pins to the analog array. switch-control logic enables selected pins to precharge continuously under hardware control. this enables capacitive measurement for applications such as touch sensing. other multiplexer applications include: track pad, finger sensing chip-wide mux that allows analog input from any i/o pin crosspoint connection between any i/o pin combinations additional system resources system resources, some of wh ich are listed in the previous sections, provide additional capability useful to complete systems. additional resources include a switch-mode pump, low-voltage detection, and power-on-reset (por). digital clock dividers provide three customizable clock frequencies for use in applications. the clocks may be routed to both the digital and analog systems. additional clocks can be generated using digital psoc blocks as clock dividers. the i 2 c module provides 100- and 400-khz communication over two wires. slave, master, and multi-master modes are all supported. lvd interrupts can signal the application of falling voltage levels, while the advanced por circuit eliminates the need for a system supervisor. an internal 1.3-v reference provides an absolute reference for the analog system, including adcs and dacs. an integrated switch-mode pump generates normal operating voltages from a single 1.2-v battery cell, providing a low cost boost converter. versatile analog mu ltiplexer system. acol1mux ace00 ace01 array array input configuration ase10 ase11 x x x x x analog mux bus all i/o aci0[1:0] aci1[1:0] [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 5 of 47 psoc device characteristics depending on your psoc device characteri stics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4 analog blocks. ta b l e 1 lists the resources available for specific psoc device groups. the psoc device covered by this datasheet is highlighted in table 1 . getting started for in-depth information, along with detailed programming details, see the psoc ? technical reference manual . for up-to-date ordering, packaging, and electrical specification information, see the latest psoc device datasheets on the web. application notes cypress application notes are an excellent introduction to the wide variety of possi ble psoc designs. development kits psoc development kits are available online from and through a growing number of regional and global distributors, which include arrow, avnet, digi-key, farnell, future electronics, and newark. training free psoc technical training (on demand, webinars, and workshops), which is available online via www.cypress.com , covers a wide variety of topics and skill levels to assist you in your designs. cypros consultants certified psoc consultants offer everything from technical assistance to completed psoc designs. to contact or become a psoc consultant go to the cypros consultants web site. solutions library visit our growing library of solution focused designs . here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. technical support technical support ? including a searchable knowledge base articles and technical forums ? is also available online. if you cannot find an answer to your question, call our technical support hotline at 1-800-541-4736. table 1. psoc device characteristics psoc part number digital i/o digital rows digital blocks analog inputs analog outputs analog columns analog blocks sram size flash size smartsense enabled cy8c29x66 up to 64 4 16 up to 12 4 4 12 2 k 32 k ? cy8c28xxx up to 44 up to 3 up to 12 up to 44 up to 4 up to 6 up to 12 + 4 [1] 1 k 16 k ? cy8c27x43 up to 44 2 8 up to 12 4 4 12 256 16 k ? cy8c24x94 up to 56 1 4 up to 48 2 2 6 1 k 16 k ? cy8c24x23a up to 24 1 4 up to 12 2 2 6 256 4 k ? cy8c23x33 up to 26 1 4 up to 12 2 2 4 256 8 k ? cy8c22x45 up to 38 2 8 up to 38 0 4 6 [1] 1 k 16 k ? cy8c21x45 up to 24 1 4 up to 24 0 4 6 [1] 512 8 k ? cy8c21x34 up to 28 1 4 up to 28 0 2 4 [1] 512 8 k ? cy8c21x34b up to 28 1 4 up to 28 0 2 4 [1] 512 8 k y cy8c21x23 up to 16 1 4 up to 8 0 2 4 [1] 256 4 k ? cy8c20x34 up to 28 0 0 up to 28 0 0 3 [1,2] 512 8 k ? cy8c20xx6a up to 36 0 0 up to 36 0 0 3 [1,2] up to 2 k up to 32 k y notes 1. limited analog functionality . 2. two analog blocks and one capsense ? . [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 6 of 47 development tools psoc designer? is the revolutionary integrated design environment (ide) that you can use to customize psoc to meet your specific application require ments. psoc designer software accelerates system design and ti me to market. develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. then, customize your design by leveraging the dynamically generated application programming interface (api) libraries of code. finally, debug and test your designs with the integrated debug environment, incl uding in-circuit emulation and standard software debug features. psoc designer includes: application editor graphical user interface (gui) for device and user module configuration and dynamic reconfiguration extensive user module catalog integrated source-code editor (c and assembly) free c compiler with no size restrictions or time limits built-in debugger in-circuit emulation built-in support for communication interfaces: ? hardware and software i 2 c slaves and masters ? full-speed usb 2.0 ? up to four full-duplex universal asynchronous receiver/transmitters (uarts), spi master and slave, and wireless psoc designer supports the entire library of psoc 1 devices and runs on windows xp, windows vista, and windows 7. psoc designer software subsystems design entry in the chip-level view, choose a base device to work with. then select different onboard analog and digital components that use the psoc blocks, which are called user modules. examples of user modules are adcs, dacs, amplifiers, and filters. configure the user modules for your chosen application and connect them to each other and to the proper pins. then generate your project. this prepopulates your project wit h apis and libraries that you can use to program your application. the tool also supports easy development of multiple configura- tions and dynamic reconfigurat ion. dynamic reconfiguration makes it possible to change configurations at run time. in essence, this allows you to use more than 100 percent of psoc's resources for an application. code generation tools the code generation tools work seamlessly within the psoc designer interface and have been tested with a full range of debugging tools. you can develop your design in c, assembly, or a combination of the two. assemblers . the assemblers allow you to merge assembly code seamlessly with c code. link libraries automatically use absolute addressing or are compiled in relative mode, and are linked with other software modules to get absolute addressing. c language compilers . c language compilers are available that support the psoc family of devices. the products allow you to create complete c programs for the psoc family devices. the optimizing c compilers provide all of the features of c, tailored to the psoc architecture. they come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. debugger psoc designer has a debug environment that provides hardware in-circuit emulation, al lowing you to test the program in a physical system while providing an internal view of the psoc device. debugger commands allow you to read and program and read and write data memory, and read and write i/o registers. you can read and write cpu registers, set and clear breakpoints, and provide program run, halt, and step control. the debugger also allows you to create a trac e buffer of registers and memory locations of interest. online help system the online help system displays on line, context-sensitive help. designed for procedural and quick reference, each functional subsystem has its own context-s ensitive help. this system also provides tutorials and links to faqs and an online support forum to aid the designer. in-circuit emulator a low-cost, high-functionality in-circuit emulator (ice) is available for development support. this hardware can program single devices. the emulator consists of a base unit that connects to the pc using a usb port. the base unit is universal and operates with all psoc devices. emulation pods for each device family are available separately. the emulat ion pod takes the place of the psoc device in the target board and performs full-speed (24 mhz) operation. [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 7 of 47 designing with psoc designer the development process for the psoc device differs from that of a traditional fixed function mi croprocessor. the configurable analog and digital hardware blocks give the psoc architecture a unique flexibility that pays divi dends in managing specification change during development and by lowering inventory costs. these configurable resources, called psoc blocks, have the ability to implement a wide variet y of user-selectable functions. the psoc development process is summarized in four steps: 1. select user modules . 2. configure user modules. 3. organize and connect. 4. generate, verify, and debug. select user modules psoc designer provides a library of prebuilt, pretested hardware peripheral components called ?user modules.? user modules make selecting and implementing peripheral devices, both analog and digital, simple. configure user modules each user module that you select establishes the basic register settings that implement the select ed function. they also provide parameters and properties that allow you to tailor their precise configuration to your particular application. for example, a pwm user module configures one or more digital psoc blocks, one for each 8 bits of resolution. the user module parameters permit you to establish the pulse width and duty cycle. configure the parameters and properties to correspond to your chosen application. enter values directly or by selecting values from drop-down menus. all the user modules are documented in datasheets that may be viewed directly in psoc designer or on the cypress website. these user module datasheets explain the internal operation of the us er module and provide performance specifications. each datasheet de scribes the use of each user module parameter, and other information you may need to successfully implement your design. organize and connect you build signal chains at the chip level by interconnecting user modules to each other and the i/o pins. you perform the selection, configuration, and rout ing so that you have complete control over all on-chip resources. generate, verify, and debug when you are ready to test the hardware configuration or move on to developing code for the project, you perform the ?generate configuration files? step. this causes psoc designer to generate source code that automatic ally configures the device to your specification and provides the software for the system. the generated code provides application programming interfaces (apis) with high-level functions to control and respond to hardware events at run-time and interrupt service routines that you can adapt as needed. a complete code development environment allows you to develop and customize your applications in either c, assembly language, or both. the last step in the development process takes place inside psoc designer?s debugger (access by clicking the connect icon). psoc designer downloads the hex image to the ice where it runs at full speed. psoc designer debugging capabilities rival those of systems costing many times more. in addition to traditional single-step, run-to-breakpoint, and watch-variable features, the debug interface provides a large trace buffer and allows you to define complex breakpoint events. these include monitoring address and data bus values, memory locations, and external signals. smartsense a key differentiation between the current offering of cy8c21x34 and cy8c21x34b, is the addition of the smartsense user module in the ?b? version. smartsense is an innovative solution from cypress that eliminates the manual tuning process from capsense applications. this solution is easy to use and provides robust noise immunity. it is the only auto-tuning solution that establishes, monitors and maintains all required tuning parameters. smartsense allows engineers to go from prototyping to mass production without re-tuning for manufacturing variations in pcb and/or overlay material properties. [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 8 of 47 pin information the cy8c21x34b psoc device is available in a variety of packages which are listed in the following tables. every port pin (labe led with a ?p?) is capable of digital i/o and c onnection to the common analog bus. however, v ss , v dd , smp, and xres are not capable of digital i/o. 16-pin part pinout figure 3. CY8C21234B 16-pin psoc device note 3. these are the issp pins, which are not high z at por. see the psoc technical reference manual for details. soic v dd p0[6], a, i, m p0[4], a, i, m p0[2], a, i, m p0[0], a, i, m p1[4], extclk, m p1[2], m p1[0], i2c sda, m 16 15 14 13 12 11 1 2 3 4 5 6 7 8 a, i, m, p0[7] a, i, m, p0[5] a, i, m, p0[3] a, i, m, p0[1] smp v ss m, i2c scl, p1[1] v ss 10 9 table 2. pin definitions ? CY8C21234B 16-pin (soic) pin no. type name description digital analog 1 i/o i, m p0[7] analog column mux input 2 i/o i, m p0[5] analog column mux input 3 i/o i, m p0[3] analog column mux input, integrating input 4 i/o i, m p0[1] analog column mux input, integrating input 5 power smp switch-mode pump (smp) connection to required external components 6 power v ss ground connection 7 i/o m p1[1] i 2 c serial clock (scl), issp-sclk [3] 8 power v ss ground connection 9 i/o m p1[0] i 2 c serial data (sda), issp-sdata [3] 10 i/o m p1[2] 11 i/o m p1[4] optional external clock input (extclk) 12 i/o i, m p0[0] analog column mux input 13 i/o i, m p0[2] analog column mux input 14 i/o i, m p0[4] analog column mux input 15 i/o i, m p0[6] analog column mux input 16 power v dd supply voltage legend a = analog, i = input, o = output, and m = analog mux input. [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 9 of 47 20-pin part pinout figure 4. cy8c21334b 20-pin psoc device note 4. these are the issp pins, which are not high z at por. see the psoc technical reference manual for details. ssop v dd p0[6], a, i, m p0[4], a, i, m p0[2], a, i, m p0[0], a, i, m xres p1[6], m p1[4], extclk, m p1[2], m p1[0], i2c sda, m 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 a, i, m, p0[7] a, i, m, p0[5] a, i, m, p0[3] a, i, m, p0[1] m, i2c scl, p1[7] m, p1[3] v ss v ss m, i2c sda, p1[5] m, i2c scl, p1[1] table 3. pin definitions ? cy8c21334b 20-pin (ssop) pin no. type name description digital analog 1 i/o i, m p0[7] analog column mux input 2 i/o i, m p0[5] analog column mux input 3 i/o i, m p0[3] analog column mux input, integrating input 4 i/o i, m p0[1] analog column mux input, integrating input 5 power v ss ground connection 6 i/o m p1[7] i 2 c scl 7 i/o m p1[5] i 2 c sda 8 i/o m p1[3] 9 i/o m p1[1] i 2 c scl, issp-sclk [4] 10 power v ss ground connection. 11 i/o m p1[0] i 2 c sda, issp-sdata [4] 12 i/o m p1[2] 13 i/o m p1[4] optional external clock input (extclk) 14 i/o m p1[6] 15 input xres active high external reset with internal pull-down 16 i/o i, m p0[0] analog column mux input 17 i/o i, m p0[2] analog column mux input 18 i/o i, m p0[4] analog column mux input 19 i/o i, m p0[6] analog column mux input 20 power v dd supply voltage legend a = analog, i = input, o = output, and m = analog mux input. [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 10 of 47 28-pin part pinout figure 5. cy8c21534b 28-pin psoc device note 5. these are the issp pins, which are not high z at por. see the psoc technical reference manual for details. a, i, m, p0[7] a, i, m, p0[5] a, i, m, p0[3] a, i, m, p0[1] m, p2[7] m, p2[5] m, p2[3] m, p2[1] v ss m, i2c scl, p1[7] m, i2c sda, p1[5] m, p1[3] m, i2c scl, p1[1] v ss v dd p0[6], a, i, m p0[4], a, i, m p0[2], a, i, m p0[0], a, i, m p2[6], m p2[4], m p2[2], m p2[0], m xres p1[6], m p1[4], extclk, m p1[2], m p1[0], i2c sda, m ssop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 table 4. pin definitions ? cy8c21534b 28-pin (ssop) pin no. type name description digital analog 1 i/o i, m p0[7] analog column mux input 2 i/o i, m p0[5] analog column mux input and column output 3 i/o i, m p0[3] analog column mux input and column output, integrating input 4 i/o i, m p0[1] analog column mux input, integrating input 5 i/o m p2[7] 6 i/o m p2[5] 7 i/o i, m p2[3] direct switched capacitor block input 8 i/o i, m p2[1] direct switched capacitor block input 9 power v ss ground connection 10 i/o m p1[7] i 2 c scl 11 i/o m p1[5] i 2 c sda 12 i/o m p1[3] 13 i/o m p1[1] i 2 c scl, issp-sclk [5] 14 power v ss ground connection 15 i/o m p1[0] i 2 c sda, issp-sdata [5] 16 i/o m p1[2] 17 i/o m p1[4] optional external clock input (extclk) 18 i/o m p1[6] 19 input xres active high external reset with internal pull-down 20 i/o i, m p2[0] direct switched capacitor block input 21 i/o i, m p2[2] direct switched capacitor block input 22 i/o m p2[4] 23 i/o m p2[6] 24 i/o i, m p0[0] analog column mux input 25 i/o i, m p0[2] analog column mux input 26 i/o i, m p0[4] analog column mux input 27 i/o i, m p0[6] analog column mux input 28 power v dd supply voltage legend a: analog, i: input, o = output, and m = analog mux input. [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 11 of 47 32-pin part pinout a, i, m, p0[1] m, p2[7] m, p2[5] m, p2[3] m, p2[1] smp qfn (top view) 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 vss p0[3], a, i, m p0[7], a, i, m vdd p0[6], a, i, m p0[4], a, i, m p0[2], a, i, m vss m, i2c scl, p1[7] p0[0], a, i, m p2[6], m p3[0], m xres m, i2c sda, p1[5] m, p1[3] m, i2c scl, p1[1] vss m, i2c sda, p1[0] m, p1[2] m, extclk, p1[4] m, p1[6] p2[4], m p2[2], m p2[0], m p3[2], m p0[5], a, i, m figure 6. cy8c21434b 32-pin psoc device fi gure 7. cy8c21634b 32-pin psoc device a, i, m, p0[1] m, p2[7] m, p2[5] m, p2[3] m, p2[1] m, p3[3] qfn (top view) 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 vss p0[3], a, i, m p0[7], a, i, m vdd p0[6], a, i, m p0[4], a, i, m p0[2], a, i, m m, p3[1] m, i2c scl, p1[7] p0[0], a, i, m p2[6], m p3[0], m xres m, i2c sda, p1[5] m, p1[3] m, i2c scl, p1[1] vss m, i2c sda, p1[0] m, p1[2] m, extclk, p1[4] m, p1[6] p2[4], m p2[2], m p2[0], m p3[2], m p0[5], a, i, m figure 8. cy8c21434b 32-pin sawn psoc device sawn figure 9. cy8c21634b 32-pin sawn psoc device [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 12 of 47 table 5. pin definitions - cy 8c21434b/cy8c21634b 32-pin (qfn) [6] pin no. type name description digital analog 1 i/o i, m p0[1] analog column mux input, integrating input 2 i/o mp2[7] 3 i/o mp2[5] 4 i/o m p2[3] 5 i/o m p2[1] 6 i/o m p3[3] in cy8c21434b part 6 power smp smp connection to required external components in cy8c21634b part 7 i/o m p3[1] in cy8c21434b part 7 power v ss ground connection in cy8c21634b part 8 i/o m p1[7] i 2 c scl 9 i/o m p1[5] i 2 c sda 10 i/o m p1[3] 11 i/o m p1[1] i 2 c scl, issp-sclk [7] 12 power v ss ground connection 13 i/o m p1[0] i 2 c sda, issp-sdata [7] 14 i/o m p1[2] 15 i/o m p1[4] optional external clock input (extclk) 16 i/o m p1[6] 17 input xres active high external reset with internal pull-down 18 i/o mp3[0] 19 i/o mp3[2] 20 i/o m p2[0] 21 i/o m p2[2] 22 i/o m p2[4] 23 i/o m p2[6] 24 i/o i, m p0[0] analog column mux input 25 i/o i, m p0[2] analog column mux input 26 i/o i, m p0[4] analog column mux input 27 i/o i, m p0[6] analog column mux input 28 power v dd supply voltage 29 i/o i, m p0[7] analog column mux input 30 i/o i, m p0[5] analog column mux input 31 i/o i, m p0[3] analog column mux input, integrating input 32 power v ss ground connection legend a = analog, i = input, o = output, and m = analog mux input. notes 6. the center pad on the qfn package must be connected to ground (v ss ) for best mechanical, thermal, and electrical performance. if not c onnected to ground, it must be electrically floated a nd not connected to any other signal. 7. these are the issp pins, which are not high z at por. see the psoc technical reference manual for details. [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 13 of 47 56-pin part pinout the 56-pin ssop part is for the cy8c21001 on-chip debug (ocd) psoc device. note this part is only used for in-circuit d ebugging. it is not available for production. figure 10. cy8c21001 56-pin psoc device table 6. pin definitions ? cy8c21001 56-pin (ssop) pin no. type pin name description digital analog 1 power v ss ground connection 2 i/o i p0[7] analog column mux input 3 i/o i p0[5] analog column mux input and column output 4 i/o i p0[3] analog column mux input and column output 5 i/o i p0[1] analog column mux input 6 i/o p2[7] 7 i/o p2[5] 8 i/o i p2[3] direct switched capacitor block input 9 i/o i p2[1] direct switched capacitor block input 10 nc no connection 11 nc no connection 12 nc no connection 13 nc no connection 14 ocd ocde ocd even data i/o 15 ocd ocdo ocd odd data output 16 power smp smp connection to required external components 17 power v ss ground connection 18 power v ss ground connection 19 i/o p3[3] ssop 1 56 vdd 2 ai, p0[7] 55 p0[6], ai 3 ai, p0[5] 54 p0[4], ai 4 ai, p0[3] 53 p0[2], ai 5 ai, p0[1] 52 p0[0], ai 6 p2[7] 51 p2[6] 7 p2[5] 50 p2[4] 8 p2[3] 49 p2[2] 9 p2[1] 48 p2[0] 10 nc 47 nc 11 nc 46 nc 12 nc 45 p3[2] 13 nc 44 p3[0] 14 ocde 43 cclk 15 ocdo 42 hclk 16 smp 41 xres 17 vss 40 nc 18 vss 39 nc 19 p3[3] 38 nc 20 p3[1] 37 nc 21 nc 36 nc 22 nc 35 nc 23 i2c scl, p1[7] 34 p1[6] 24 i2c sda, p1[5] 33 p1[4], extclk 25 nc 32 p1[2] 26 p1[3] 31 p1[0], i2c sda, sdata 27 sclk, i2c scl, p1[1] 30 nc 28 vss 29 nc vss [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 14 of 47 20 i/o p3[1] 21 nc no connection 22 nc no connection 23 i/o p1[7] i 2 c scl 24 i/o p1[5] i 2 c sda 25 nc no connection 26 i/o p1[3] i fmtest 27 i/o p1[1] i 2 c scl, issp-sclk [8] 28 power v ss ground connection 29 nc no connection 30 nc no connection 31 i/o p1[0] i 2 c sda, issp-sdata [8] 32 i/o p1[2] v fmtest 33 i/o p1[4] optional external clock input (extclk) 34 i/o p1[6] 35 nc no connection 36 nc no connection 37 nc no connection 38 nc no connection 39 nc no connection 40 nc no connection 41 input xres active high external reset with internal pull-down 42 ocd hclk ocd high-speed clock output 43 ocd cclk ocd cpu clock output 44 i/o p3[0] 45 i/o p3[2] 46 nc no connection 47 nc no connection 48 i/o ip2[0] 49 i/o ip2[2] 50 i/o p2[4] 51 i/o p2[6] 52 i/o i p0[0] analog column mux input 53 i/o i p0[2] analog column mux input and column output 54 i/o i p0[4] analog column mux input and column output 55 i/o i p0[6] analog column mux input 56 power v dd supply voltage legend : a = analog, i = input, o = output, and ocd = on-chip debug. table 6. pin definitions ? cy8c21001 56-pin (ssop) (continued) pin no. type pin name description digital analog note 8. these are the issp pins, which are not high z at por. see the psoc technical reference manual for details. [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 15 of 47 register reference this chapter lists the registers of the cy8c21x34b pso c device. for detailed register information, see the psoc technical reference manual . register conventions the register conventions specific to this section are listed in ta b l e 7 . register mapping tables the psoc device has a total register address space of 512 bytes. the register space is referred to as i/o space and is divided into two banks, bank 0 and bank 1. the xoi bit in the flag register (cpu_f) determines which bank the user is currently in. when the xoi bit is set to 1, the user is in bank 1. note in the following register mapping tables, blan k fields are reserved and must not be accessed. table 7. register conventions convention description r read register or bit(s) w write register or bit(s) l logical register or bit(s) c clearable register or bit(s) # access is bit specific [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 16 of 47 table 8. register map 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw 40 ase10cr0 80 rw c0 prt0ie 01 rw 41 81 c1 prt0gs 02 rw 42 82 c2 prt0dm2 03 rw 43 83 c3 prt1dr 04 rw 44 ase11cr0 84 rw c4 prt1ie 05 rw 45 85 c5 prt1gs 06 rw 46 86 c6 prt1dm2 07 rw 47 87 c7 prt2dr 08 rw 48 88 c8 prt2ie 09 rw 49 89 c9 prt2gs 0a rw 4a 8a ca prt2dm2 0b rw 4b 8b cb prt3dr 0c rw 4c 8c cc prt3ie 0d rw 4d 8d cd prt3gs 0e rw 4e 8e ce prt3dm2 0f rw 4f 8f cf 10 50 90 cur_pp d0 rw 11 51 91 stk_pp d1 rw 12 52 92 d2 13 53 93 idx_pp d3 rw 14 54 94 mvr_pp d4 rw 15 55 95 mvw_pp d5 rw 16 56 96 i2c_cfg d6 rw 17 57 97 i2c_scr d7 # 18 58 98 i2c_dr d8 rw 19 59 99 i2c_mscr d9 # 1a 5a 9a int_clr0 da rw 1b 5b 9b int_clr1 db rw 1c 5c 9c dc 1d 5d 9d int_clr3 dd rw 1e 5e 9e int_msk3 de rw 1f 5f 9f df dbb00dr0 20 # amx_in 60 rw a0 int_msk0 e0 rw dbb00dr1 21 w amuxcfg 61 rw a1 int_msk1 e1 rw dbb00dr2 22 rw pwm_cr 62 rw a2 int_vc e2 rc dbb00cr0 23 # 63 a3 res_wdt e3 w dbb01dr0 24 # cmp_cr0 64 # a4 e4 dbb01dr1 25 w 65 a5 e5 dbb01dr2 26 rw cmp_cr1 66 rw a6 dec_cr0 e6 rw dbb01cr0 27 # 67 a7 dec_cr1 e7 rw dcb02dr0 28 # adc0_cr 68 # a8 e8 dcb02dr1 29 w adc1_cr 69 # a9 e9 dcb02dr2 2a rw 6a aa ea dcb02cr0 2b # 6b ab eb dcb03dr0 2c # tmp_dr0 6c rw ac ec dcb03dr1 2d w tmp_dr1 6d rw ad ed dcb03dr2 2e rw tmp_dr2 6e rw ae ee dcb03cr0 2f # tmp_dr3 6f rw af ef 30 70 rdi0ri b0 rw f0 31 71 rdi0syn b1 rw f1 32 ace00cr1 72 rw rdi0is b2 rw f2 33 ace00cr2 73 rw rdi0lt0 b3 rw f3 34 74 rdi0lt1 b4 rw f4 35 75 rdi0ro0 b5 rw f5 36 ace01cr1 76 rw rdi0ro1 b6 rw f6 37 ace01cr2 77 rw b7 cpu_f f7 rl 38 78 b8 f8 39 79 b9 f9 3a 7a ba fa 3b 7b bb fb 3c 7c bc fc 3d 7d bd dac_d fd rw 3e 7e be cpu_scr1 fe # 3f 7f bf cpu_scr0 ff # blank fields are reserved and must not be accessed. # access is bit specific. [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 17 of 47 table 9. register map 1 table: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 00 rw 40 ase10cr0 80 rw c0 prt0dm1 01 rw 41 81 c1 prt0ic0 02 rw 42 82 c2 prt0ic1 03 rw 43 83 c3 prt1dm0 04 rw 44 ase11cr0 84 rw c4 prt1dm1 05 rw 45 85 c5 prt1ic0 06 rw 46 86 c6 prt1ic1 07 rw 47 87 c7 prt2dm0 08 rw 48 88 c8 prt2dm1 09 rw 49 89 c9 prt2ic0 0a rw 4a 8a ca prt2ic1 0b rw 4b 8b cb prt3dm0 0c rw 4c 8c cc prt3dm1 0d rw 4d 8d cd prt3ic0 0e rw 4e 8e ce prt3ic1 0f rw 4f 8f cf 10 50 90 gdi_o_in d0 rw 11 51 91 gdi_e_in d1 rw 12 52 92 gdi_o_ou d2 rw 13 53 93 gdi_e_ou d3 rw 14 54 94 d4 15 55 95 d5 16 56 96 d6 17 57 97 d7 18 58 98 mux_cr0 d8 rw 19 59 99 mux_cr1 d9 rw 1a 5a 9a mux_cr2 da rw 1b 5b 9b mux_cr3 db rw 1c 5c 9c dc 1d 5d 9d osc_go_en dd rw 1e 5e 9e osc_cr4 de rw 1f 5f 9f osc_cr3 df rw dbb00fn 20 rw clk_cr0 60 rw a0 osc_cr0 e0 rw dbb00in 21 rw clk_cr1 61 rw a1 osc_cr1 e1 rw dbb00ou 22 rw abf_cr0 62 rw a2 osc_cr2 e2 rw 23 amd_cr0 63 rw a3 vlt_cr e3 rw dbb01fn 24 rw cmp_go_en 64 rw a4 vlt_cmp e4 r dbb01in 25 rw 65 a5 adc0_tr e5 rw dbb01ou 26 rw amd_cr1 66 rw a6 adc1_tr e6 rw 27 alt_cr0 67 rw a7 e7 dcb02fn 28 rw 68 a8 imo_tr e8 w dcb02in 29 rw 69 a9 ilo_tr e9 w dcb02ou 2a rw 6a aa bdg_tr ea rw 2b clk_cr3 6b rw ab eco_tr eb w dcb03fn 2c rw tmp_dr0 6c rw ac ec dcb03in 2d rw tmp_dr1 6d rw ad ed dcb03ou 2e rw tmp_dr2 6e rw ae ee 2f tmp_dr3 6f rw af ef 30 70 rdi0ri b0 rw f0 31 71 rdi0syn b1 rw f1 32 ace00cr1 72 rw rdi0is b2 rw f2 33 ace00cr2 73 rw rdi0lt0 b3 rw f3 34 74 rdi0lt1 b4 rw f4 35 75 rdi0ro0 b5 rw f5 36 ace01cr1 76 rw rdi0ro1 b6 rw f6 37 ace01cr2 77 rw b7 cpu_f f7 rl 38 78 b8 f8 39 79 b9 f9 3a 7a ba fls_pr1 fa rw 3b 7b bb fb 3c 7c bc fc 3d 7d bd dac_cr fd rw 3e 7e be cpu_scr1 fe # 3f 7f bf cpu_scr0 ff # blank fields are reserved and must not be accessed. # access is bit specific. [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 18 of 47 electrical specifications this section presents the dc and ac electr ical specifications of the cy8c21x34b pso c device. for up-to-date electrical specific a- tions, visit the cy press web site at http://www.cypress.com . specifications are valid for ?40 c t a 85 c and t j 100 c as specified, except where noted. refer to table 21 on page 25 for the electrical specificatio ns for the imo using slimo mode. absolute maximum ratings symbol description min typ max units notes t stg storage temperature ?55 25 +100 c higher storage temperatures reduce data retention time. recommended storage temperature is +25 c 25 c. extended duration storage temperatures above 65 c degrade reliability. t baketemp bake temperature ? 125 see package label c t baketime bake time see package label ? 72 hours t a ambient temperature with power applied ?40 ? +85 c v dd supply voltage on v dd relative to v ss ?0.5 ? +6.0 v v io dc input voltage v ss ? 0.5 ? v dd + 0.5 v v ioz dc voltage applied to tri-state v ss ? 0.5 ? v dd + 0.5 v i mio maximum current into any port pin ?25 ? +50 ma esd electrostatic discharge voltage 2000 ? ? v human body model esd. lu latch-up current ? ? 200 ma figure 11. voltage versus cpu frequency figure 14. imo frequency trim options 5.25 4.75 3.00 93 khz 12 mhz 24 mhz cpu frequency vdd voltage 5.25 4.75 3.00 93 khz 12 mhz 24 mhz imo frequency vdd voltage 3.60 6 mhz slimo mode = 0 slimo mode=0 2.40 slimo mode=1 slimo mode=1 slimo mode=1 2.40 3 mhz v a l i d o p e r a t i n g r e g i o n slimo mode=1 slimo mode=0 [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 19 of 47 operating temperature dc electrical characteristics dc chip-level specifications ta b l e 1 0 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, 3.0 v to 3.6 v and ?40 c t a 85 c, or 2.4 v to 3.0 v and ?40 c t a 85 c, respectively. typical parameters are measured at 5 v, 3.3 v, or 2.7 v at 25 c and are for design guidance only. symbol description min typ max units notes t a ambient temperature ?40 ? +85 c t j junction temperature ?40 ? +100 c the temperature rise from ambient to junction is package specific. see ta b l e 34 on page 36 . you must limit the power consumption to comply with this requirement. table 10. dc chip-level specifications symbol description min typ max units notes v dd supply voltage 2.40 ? 5.25 v see table 18 on page 23 i dd supply current, imo = 24 mhz ? 3 4 ma conditions are v dd = 5.0 v, t a = 25 c, cpu = 3 mhz, 48 mhz disabled. vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 0.366 khz i dd3 supply current, imo = 6 mhz using slimo mode. ? 1.2 2 ma conditions are v dd = 3.3 v, t a = 25 c, cpu = 3 mhz, clock doubler disabled. vc1 = 375 khz, vc2 = 23.4 khz, vc3 = 0.091 khz i dd27 supply current, imo = 6 mhz using slimo mode. ? 1.1 1.5 ma conditions are v dd = 2.55 v, t a = 25 c, cpu = 3 mhz, clock doubler disabled. vc1 = 375 khz, vc2 = 23.4 khz, vc3 = 0.091 khz i sb27 sleep (mode) current with por, lvd, sleep timer, wdt, and internal slow oscillator active. mid temperature range. ? 2.6 4 a v dd = 2.55 v, 0 c t a 40 c i sb sleep (mode) current with por, lvd, sleep timer, wdt, and internal slow oscillator active. ? 2.8 5 a v dd = 3.3 v, ?40 c t a 85 c v ref reference voltage (bandgap) 1.28 1.30 1.32 v trimmed for appropriate v dd v dd = 3.0 v to 5.25 v v ref27 reference voltage (bandgap) 1.16 1.30 1.33 v trimmed for appropriate v dd v dd = 2.4 v to 3.0 v agnd analog ground v ref ? 0.003 v ref v ref + 0.003 v [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 20 of 47 dc general-purpose i/o specifications the following tables list the guaranteed maximum and minimum specif ications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, 3.0 v to 3.6 v and ?40 c t a 85 c, or 2.4 v to 3.0 v and ?40 c t a 85 c, respectively. typical parameters are measured at 5 v, 3.3 v, and 2.7 v at 25 c and are for design guidance only. table 11. 5-v and 3.3-v dc gpio specifications symbol description min typ max units notes r pu pull-up resistor 4 5.6 8 k r pd pull-down resistor 4 5.6 8 k v oh high output level v dd ? 1.0 ? ? v i oh = 10 ma, v dd = 4.75 to 5.25 v (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0[3], p1[5]) v ol low output level ? ? 0.75 v i ol = 25 ma, v dd = 4.75 to 5.25 v (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0[3], p1[5])) i oh high level source current 10 ? ? ma v oh = v dd ? 1.0 v, see the limitations of the total current in the note for v oh i ol low level sink current 25 ? ? ma v ol = 0.75 v, see the limitations of the total current in the note for v ol v il input low level ? ? 0.8 v v dd = 3.0 to 5.25 v ih input high level 2.1 ? v v dd = 3.0 to 5.25 v h input hysteresis ? 60 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 a c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent te m p = 2 5 c c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent te m p = 2 5 c table 12. 2.7-v dc gpio specifications symbol description min typ max units notes r pu pull-up resistor 4 5.6 8 k r pd pull-down resistor 4 5.6 8 k v oh high output level v dd ? 0.4 ? ? v i oh = 2.5 ma (6.25 typ), v dd = 2.4 to 3.0 v (16 ma maximum, 50 ma typ combined i oh budget) v ol low output level ? ? 0.75 v i ol = 10 ma, v dd = 2.4 to 3.0 v (90 ma maximum combined i ol budget) i oh high level source current 2.5 ? ? ma v oh = v dd ? 0.4 v, see the limitations of the total current in the note for v oh i ol low level sink current 10 ? ? ma v ol = 0.75 v, see the limitations of the total current in the note for v ol v il input low level ? ? 0.75 v v dd = 2.4 to 3.0 v ih input high level 2.0 ? ? v v dd = 2.4 to 3.0 v h input hysteresis ? 90 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 a c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent te m p = 2 5 c c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent te m p = 2 5 c [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 21 of 47 dc operational amplifier specifications the following tables list the guaranteed maximum and minimum specif ications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, 3.0 v to 3.6 v and ?40 c t a 85 c, or 2.4 v to 3.0 v and ?40 c t a 85 c, respectively. typical parameters are measured at 5 v, 3.3 v, or 2.7 v at 25 c and are for design guidance only. table 13. 5-v dc operational amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) ? 2.5 15 mv tcv osoa average input offset voltage drift ? 10 ? v/c i eboa input leakage current (port 0 analog pins 7-to-1) ? 200 ? pa gross tested to 1 a i eboa00 input leakage current (port 0, pin 0 analog pin) ? 50 ? na gross tested to 1 a c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. te m p = 2 5 c v cmoa common mode voltage range 0.0 ? v dd ? 1.0 v g oloa open loop gain ? 80 ? db i soa amplifier supply current ? 10 30 a table 14. 3.3-v dc operatio nal amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) ? 2.5 15 mv tcv osoa average input offset voltage drift ? 10 ? v/c i eboa input leakage current (port 0 analog pins) ? 200 ? pa gross tested to 1 a i eboa00 input leakage current (port 0, pin 0 analog pin) ? 50 ? na gross tested to 1 a c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. temp = 25 c v cmoa common mode voltage range 0 ? v dd ? 1.0 v g oloa open loop gain ? 80 ? db i soa amplifier supply current ? 10 30 a table 15. 2.7-v dc operatio nal amplifier specifications symbol description min typ max units notes v osoa input offset voltage (absolute value) ? 2.5 15 mv tcv osoa average input offset voltage drift ? 10 ? v/c i eboa input leakage current (port 0 analog pins) ? 200 ? pa gross tested to 1 a i eboa00 input leakage current (port 0, pin 0 analog pin) ? 50 ? na gross tested to 1 a c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. temp = 25 c v cmoa common mode voltage range 0 ? v dd ? 1.0 v g oloa open loop gain ? 80 ? db i soa amplifier supply current ? 10 30 a [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 22 of 47 dc switch mode pump specifications ta b l e 1 6 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, 3.0 v to 3.6 v and ?40 c t a 85 c, or 2.4 v to 3.0 v and ?40 c t a 85 c, respectively. typical parameters are measured at 5 v, 3.3 v, or 2.7 v at 25 c and are for design guidance only. figure 12. basic switch mode pump circuit table 16. dc switch mode pump (smp) specifications symbol description min typ max units notes v pump5v 5 v output voltage from pump 4.75 5.0 5.25 v configured as in note 9 average, neglecting ripple smp trip voltage is set to 5.0 v v pump3v 3.3 v output voltage from pump 3.00 3.25 3.60 v configured as in note 9 average, neglecting ripple. smp trip voltage is set to 3.25 v v pump2v 2.6 v output voltage from pump 2.45 2.55 2.80 v configured as in note 9 average, neglecting ripple. smp trip voltage is set to 2.55 v i pump available output current v bat = 1.8 v, v pump = 5.0 v v bat = 1.5 v, v pump = 3.25 v v bat = 1.3 v, v pump = 2.55 v 5 8 8 ? ? ? ? ? ? ma ma ma configured as in note 9 smp trip voltage is set to 5.0 v smp trip voltage is set to 3.25 v smp trip voltage is set to 2.55 v v bat5v input voltage range from battery 1.8 ? 5.0 v configured as in note 9 smp trip voltage is set to 5.0 v v bat3v input voltage range from battery 1.0 ? 3.3 v configured as in note 9 smp trip voltage is set to 3.25 v v bat2v input voltage range from battery 1.0 ? 2.8 v configured as in note 9 smp trip voltage is set to 2.55 v v batstart minimum input voltage from battery to start pump 1.2 ? ? v configured as in note 9 0 c t a 100. 1.25 v at t a = ?40 c v pump_line line regulation (over vi range) ? 5 ? %v o configured as in note 9 v o is the ?v dd value for pump trip? specified by the vm[2:0] setting in the dc por and lvd specification, table 18 on page 23 v pump_load load regulation ? 5 ? %v o configured as in note 9 v o is the ?v dd value for pump trip? specified by the vm[2:0] setting in the dc por and lvd specification, table 18 on page 23 battery c1 d1 + psoc vdd vss smp v bat l 1 v pump note 9. l 1 = 2 mh inductor, c 1 = 10 mf capacitor, d 1 = schottky diode. see figure 12 . [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 23 of 47 dc analog mux bus specifications ta b l e 1 7 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, 3.0 v to 3.6 v and ?40 c t a 85 c, or 2.4 v to 3.0 v and ?40 c t a 85 c, respectively. typical parameters are measured at 5 v, 3.3 v, or 2.7 v at 25 c and are for design guidance only. dc por and lvd specifications ta b l e 1 8 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, 3.0 v to 3.6 v and ?40 c t a 85 c, or 2.4 v to 3.0 v and ?40 c t a 85 c, respectively. typical parameters are measured at 5 v, 3.3 v, or 2.7 v at 25 c and are for design guidance only. v pump_ripple output voltage ripple (depends on cap/load) ? 100 ? mvpp configured as in note 9 load is 5 ma e 3 efficiency 35 50 ? % configured as in note 9 load is 5 ma. smp trip voltage is set to 3.25 v e 2 efficiency 35 80 ? % for i load = 1ma, v pump = 2.55 v, v bat = 1.3 v, 10 h inductor, 1 f capacitor, and schottky diode f pump switching frequency ? 1.3 ? mhz dc pump switching duty cycle ? 50 ? % table 16. dc switch mode pump (smp) specifications (continued) symbol description min typ max units notes table 17. dc analog mux bus specifications symbol description min typ max units notes r sw switch resistance to common analog bus ? ? 400 800 v dd 2.7 v 2.4 v v dd 2.7 v r vdd resistance of initialization switch to v dd ? ? 800 table 18. dc por and lvd specifications symbol description min typ max units notes v ppor0 v ppor1 v ppor2 v dd value for ppor trip porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? ? ? 2.36 2.82 4.55 2.40 2.95 4.70 v v v v dd must be greater than or equal to 2.5 v during startup, the reset from the xres pin, or reset from watchdog v lvd0 v lvd1 v lvd2 v lvd3 v lvd4 v lvd5 v lvd6 v lvd7 v dd value for lvd trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.40 2.85 2.95 3.06 4.37 4.50 4.62 4.71 2.45 2.92 3.02 3.13 4.48 4.64 4.73 4.81 2.51 [10] 2.99 [11] 3.09 3.20 4.55 4.75 4.83 4.95 v v v v v v v v v pump0 v pump1 v pump2 v pump3 v pump4 v pump5 v pump6 v pump7 v dd value for pump trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.45 2.96 3.03 3.18 4.54 4.62 4.71 4.89 2.55 3.02 3.10 3.25 4.64 4.73 4.82 5.00 2.62 [12] 3.09 3.16 3.32 [13] 4.74 4.83 4.92 5.12 v v v v v v v v notes 10. always greater than 50 mv above v ppor (porlev = 00) for falling supply. 11. always greater than 50 mv above v ppor (porlev = 01) for falling supply. 12. always greater than 50 mv above v lvd0 . 13. always greater than 50 mv above v lvd3 . [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 24 of 47 dc programming specifications ta b l e 1 9 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, 3.0 v to 3.6 v and ?40 c t a 85 c, or 2.4 v to 3.0 v and ?40 c t a 85 c, respectively. typical parameters are measured at 5 v, 3.3 v, or 2.7 v at 25 c and are for design guidance only. dc i 2 c specifications ta b l e 2 0 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, 3.0 v to 3.6 v and ?40 c t a 85 c, or 2.4 v to 3.0 v and ?40 c t a 85 c, respectively. typical parameters are measured at 5 v, 3.3 v, or 2.7 v at 25 c and are for design guidance only. table 19. dc programming specifications symbol description min typ max units notes v ddp v dd for programming and erase 4.5 5 5.5 v this specification applies to the functional requirements of external programmer tools v ddlv low v dd for verify 2.4 2.5 2.6 v this specification applies to the functional requirements of external programmer tools v ddhv high v dd for verify 5.1 5.2 5.3 v this specification applies to the functional requirements of external programmer tools v ddiwrite supply voltage for flash write operation 2.7 5.25 v this specification applies to this device when it is executing internal flash writes i ddp supply current during programming or verify ? 5 25 ma v ilp input low voltage during programming or verify ? ? 0.8 v v ihp input high voltage during programming or verify 2.2 ? ? v i ilp input current when applying v ilp to p1[0] or p1[1] during programming or verify ? ? 0.2 ma driving internal pull-down resistor i ihp input current when applying v ihp to p1[0] or p1[1] during programming or verify ? ? 1.5 ma driving internal pull-down resistor v olv output low voltage during programming or verify ? ? v ss + 0.75 v v ohv output high voltage during programming or verify v dd ? 1.0 ? v dd v flash enpb flash endurance (per block) 50,000 [14] ? ? ? erase/write cycles per block flash ent flash endurance (total) [15] 1,800,000 ? ? ? erase/write cycles flash dr flash data retention 10 ? ? years table 20. dc i 2 c specifications [16] symbol description min typ max units notes v ili2c input low level ? ? 0.3 v dd v 2.4 v v dd 3.6 v ? ? 0.25 v dd v 4.75 v v dd 5.25 v v ihi2c input high level 0.7 v dd ? ? v 2.4 v v dd 5.25 v notes 14. the 50,000 cycle flash endurance per block is only guaranteed if the flash is operating within one voltage range. voltage ra nges are 2.4 v to 3.0 v, 3.0 v to 3.6 v, and 4.75 v to 5.25 v. 15. a maximum of 36 50,000 block endurance cycles is allowed. this may be balanced between operat ions on 36 1 blocks of 50,0 00 maximum cycles each, 362 blocks of 25,000 maximum cy cles each, or 36 4 blocks of 12,500 maximum cycl es each (to limit the total number of cycles to 36 50,000 and ensure that no single block ever sees more than 50,000 c ycles). for the full industrial range, you mu st employ a temperature sensor user modul e (flashtemp) and feed the result to the temperature argument before writing. refer to t he flash apis application note an2015 (design aids - reading and writing psoc ? flash) for more information. 16. all gpio meet the dc gpio vil and vih specifications found in the dc gpio spec ifications sections. the i 2 c gpio pins also meet the above specs. [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 25 of 47 ac electrical characteristics ac chip-level specifications the following tables list the guaranteed maximum and minimum specif ications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, 3.0 v to 3.6 v and ?40 c t a 85 c, or 2.4 v to 3.0 v and ?40 c t a 85 c, respectively. typical parameters are measured at 5 v, 3.3 v, or 2.7 v at 25 c and are for design guidance only. table 21. 5-v and 3.3-v ac chip-level specifications symbol description min typ max units notes f imo24 imo frequency for 24 mhz 23.4 24 24.6 [17,18] mhz trimmed for 5 v or 3.3 v operation using factory trim values. see figure 14 on page 18 . slimo mode = 0 f imo6 imo frequency for 6 mhz 5.5 6 6.5 [17,18] mhz trimmed for 5 v or 3.3 v operation using factory trim values. see figure 14 on page 18 . slimo mode = 1 f cpu1 cpu frequency (5 v nominal) 0.091 24 24.6 [17] mhz 24 mhz only for slimo mode = 0 f cpu2 cpu frequency (3.3 v nominal) 0.091 12 12.3 [18] mhz slimo mode = 0 f blk5 digital psoc block frequency 0 (5 v nominal) 0 48 49.2 [17,19] mhz refer to ac digital block specifications on page 28 f blk33 digital psoc block frequency (3.3 v nominal) 0 24 24.6 [19] mhz f 32k1 ilo frequency 15 32 64 khz f 32k_u ilo untrimmed frequency 5 ? 100 khz after a reset and before the m8c starts to run, the ilo is not trimmed. see the system resets section of the psoc technical reference manual for details on this timing t xrst external reset pulse width 10 ? ? s dc24m 24 mhz duty cycle 40 50 60 % dc ilo ilo duty cycle 20 50 80 % step24m 24 mhz trim step size ? 50 ? khz fout48m 48 mhz output frequency 46.8 48.0 49.2 [17,18] mhz trimmed. using factory trim values f max maximum frequency of signal on row input or row output. ? ? 12.3 mhz sr power_up power supply slew rate ? ? 250 v/ms v dd slew rate during power-up t powerup time from end of por to cpu executing code ? 16 100 ms power-up from 0 v. see the system resets section of the psoc technical reference manual t jit_imo 24-mhz imo cycle-to- cycle jitter (rms) [20] ?200 700 ps 24-mhz imo long term n cycle-to-cycle jitter (rms) [20] ? 300 900 ps n = 32 24-mhz imo period jitter (rms) [20] ?100 400 ps notes 17. 4.75 v < v dd < 5.25 v. 18. 3.0 v < v dd < 3.6 v. see application note an2012 ?adjusting psoc microcontroller trims for dual voltage-range operation? for information on trimming for operation at 3.3 v. 19. see the individual user module datasheets for information on maximum frequencies for user modules. 20. refer to cypress jitter specifications application note an5054 ?understanding datasheet jitt er specifications for cypr ess timing products? at www.cypress.com under application notes for more information. [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 26 of 47 note 21. 2.4 v < v dd < 3.0 v. 22. see application note an2012 ?adjusting psoc microcontroller trims for d ual voltage-range operation? available at http://www.cypress.com for information on maximum frequency for user modules. 23. refer to cypress jitter specifications application note an5054 ?understanding datasheet jitt er specifications for cypr ess timing products? at www.cypress.com under application notes for more information. table 22. 2.7-v ac chip-level specifications symbol description min typ max units notes f imo12 imo frequency for 12 mhz 11.5 12 0 12.7 [21,22] mhz trimmed for 2.7 v operation using factory trim values. see figure 14 on page 18 . slimo mode = 1 f imo6 imo frequency for 6 mhz 5.5 6 6.5 [21,22] mhz trimmed for 2.7 v operation using factory trim values. see figure 14 on page 18 . slimo mode = 1 f cpu1 cpu frequency (2.7 v nominal) 0.093 3 3.15 [21] mhz 12 mhz only for slimo mode = 0 f blk27 digital psoc block frequency (2.7 v nominal) 0 12 12.5 [21,22] mhz refer to ac digital block specifications on page 28 f 32k1 ilo frequency 8 32 96 khz f 32k_u ilo untrimmed frequency 5 ? 100 khz after a reset and before the m8c starts to run, the ilo is not trimmed. see the system resets section of the psoc technical reference manual for details on this timing t xrst external reset pulse width 10 ? ? s dc ilo iilo duty cycle 20 50 80 % f max maximum frequency of signal on row input or row output. ? ? 12.3 mhz sr power_up power supply slew rate ? ? 250 v/ms v dd slew rate during power-up t powerup time from end of por to cpu executing code ? 16 100 ms power-up from 0 v. see the system resets section of the psoc technical reference manual . t jit_imo 12 mhz imo cycle-to-cycle jitter (rms) [23] ? 400 1000 ps 12 mhz imo long term n cycle-to-cycle jitter (rms) [23] ? 600 1300 ps n = 32 12 mhz imo period jitter (rms) [23] ? 100 500 ps [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 27 of 47 ac general purpose i/o specifications the following tables list the guaranteed maximum and minimum specif ications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, 3.0 v to 3.6 v and ?40 c t a 85 c, or 2.4 v to 3.0 v and ?40 c t a 85 c, respectively. typical parameters are measured at 5 v, 3.3 v, or 2.7 v at 25 c and are for design guidance only. figure 13. gpio timing diagram ac operational amplifier specifications ta b l e 2 5 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, 3.0 v to 3.6 v and ?40 c t a 85 c, or 2.4 v to 3.0 v and ?40 c t a 85 c, respectively. typical parameters are measured at 5 v, 3.3 v, or 2.7 v at 25 c and are for design guidance only. table 23. 5-v and 3.3-v ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 12 mhz normal strong mode trisef rise time, normal strong mode, cload = 50 pf 3 ? 18 ns v dd = 4.5 to 5.25 v, 10% to 90% tfallf fall time, normal strong mode, cload = 50 pf 2 ? 18 ns v dd = 4.5 to 5.25 v, 10% to 90% trises rise time, slow strong mode, cload = 50 pf 7 27 ? ns v dd = 3 to 5.25 v, 10% to 90% tfalls fall time, slow strong mode, cload = 50 pf 7 22 ? ns v dd = 3 to 5.25 v, 10% to 90% table 24. 2.7 v ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 3 mhz normal strong mode trisef rise time, normal strong mode, cload = 50 pf 6 ? 50 ns v dd = 2.4 to 3.0 v, 10% to 90% tfallf fall time, normal strong mode, cload = 50 pf 6 ? 50 ns v dd = 2.4 to 3.0 v, 10% to 90% trises rise time, slow strong mode, cload = 50 pf 18 40 120 ns v dd = 2.4 to 3.0 v, 10% to 90% tfalls fall time, slow strong mode, cload = 50 pf 18 40 120 ns v dd = 2.4 to 3.0 v, 10% to 90% tfallf tfalls tris ef trises 90% 10% gpio pin output voltage table 25. ac operational amplifier specifications symbol description min typ max units notes t comp comparator mode response time, 50 mv overdrive ??100 200 ns ns v dd 3.0 v 2.4 v < v cc < 3.0 v [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 28 of 47 ac digital block specifications the following tables list the guaranteed maximum and minimum specif ications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, 3.0 v to 3.6 v and ?40 c t a 85 c, or 2.4 v to 3.0 v and ?40 c t a 85 c, respectively. typical parameters are measured at 5 v, 3.3 v, or 2.7 v at 25 c and are for design guidance only. table 26. 5-v and 3.3-v ac digital block specifications function description min typ max unit notes all functions block input clock frequency v dd 4.75 v ? ? 49.2 mhz v dd < 4.75 v ? ? 24.6 mhz timer input clock frequency no capture, v dd 4.75 v ? ? 49.2 mhz no capture, v dd < 4.75 v ? ? 24.6 mhz with capture ? ? 24.6 mhz capture pulse width 50 [24] ??ns counter input clock frequency no enable input, v dd 4.75 v ? ? 49.2 mhz no enable input, v dd < 4.75 v ? ? 24.6 mhz with enable input ? ? 24.6 mhz enable input pulse width 50 [24] ??ns dead band kill pulse width asynchronous restart mode 20 ? ? ns synchronous restart mode 50 [24] ??ns disable mode 50 [24] ??ns input clock frequency v dd 4.75 v ? ? 49.2 mhz v dd < 4.75 v ? ? 24.6 mhz crcprs (prs mode) input clock frequency v dd 4.75 v ? ? 49.2 mhz v dd < 4.75 v ? ? 24.6 mhz crcprs (crc mode) input clock frequency ? ? 24.6 mhz spim input clock frequency ? ? 8.2 mhz the spi serial clock (sclk) frequency is equal to the input clock frequency divided by 2. spis input clock (sclk) frequency ? ? 4.1 mhz the i nput clock is the spi sclk in spis mode. width of ss_negated between transmissions 50 [24] ??ns transmitter input clock frequency the baud rate is equal to the input clock frequency divided by 8. v dd 4.75 v, 2 stop bits ? ? 49.2 mhz v dd 4.75 v, 1 stop bit ? ? 24.6 mhz v dd < 4.75 v ? ? 24.6 mhz receiver input clock frequency the baud rate is equal to the input clock frequency divided by 8. v dd 4.75 v, 2 stop bits ? ? 49.2 mhz v dd 4.75 v, 1 stop bit ? ? 24.6 mhz v dd < 4.75 v ? ? 24.6 mhz note 24. 50 ns minimum input pulse width is based on the input synchronizers running at 24 mhz (42 ns nominal period). [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 29 of 47 ac external clock specifications the following tables list the guaranteed maximum and minimum specif ications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters are measured at 5 v, 3.3 v, or 2.7 v at 25 c and are for design guidance only. table 27. 2.7-v ac digital block specifications function description min typ max units notes all functions block input clock frequency ? ? 12.7 mhz 2.4 v < v dd < 3.0 v timer capture pulse width 100 [25] ? ? ns input clock frequency, with or without capture ? ? 12.7 mhz counter enable input pulse width 100 ? ? ns input clock frequency, no enable input ? ? 12.7 mhz input clock frequency, enable input ? ? 12.7 mhz dead band kill pulse width: asynchronous restart mode 20 ? ? ns synchronous restart mode 100 ? ? ns disable mode 100 ? ? ns input clock frequency ? ? 12.7 mhz crcprs (prs mode) input clock frequency ? ? 12.7 mhz crcprs (crc mode) input clock frequency ? ? 12.7 mhz spim input clock frequency ? ? 6.35 mhz the spi serial clock (sclk) frequency is equal to the input clock frequency divided by 2. spis input clock (sclk) frequency ? ? 4.1 mhz width of ss_ negated between transmissions 100 ? ? ns transmitter input clock frequency ? ? 12.7 mhz the baud rate is equal to the input clock frequency divided by 8. receiver input clock frequency ? ? 12.7 mhz the baud rate is equal to the input clock frequency divided by 8. table 28. 5-v ac external clock specifications symbol description min typ max units notes f oscext frequency 0.093 ?24.6mhz ? high period 20.6 ? 5300 ns ? low period 20.6 ? ?ns ? power-up imo to switch 150 ? ?s note 25. 100 ns minimum input pulse width is based on the input synchronizers running at 12 mhz (84 ns nominal period). [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 30 of 47 table 29. 3.3-v ac external clock specifications symbol description min typ max units notes f oscext frequency with cpu clock divide by 1 0.093 ? 12.3 mhz maximum cpu frequency is 12 mhz at 3.3 v. with the cpu clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements f oscext frequency with cpu clock divide by 2 or greater 0.186 ? 24.6 mhz if the frequency of the external clock is greater than 12 mhz, the cpu clock divider must be set to 2 or greater. in this case, the cpu clock divider ensures that the fifty percent duty cycle requirement is met ? high period with cpu clock divide by 1 41.7 ? 5300 ns ? low period with cpu clock divide by 1 41.7 ? ?ns ? power-up imo to switch 150 ? ?s table 30. 2.7-v ac external clock specifications symbol description min typ max units notes f oscext frequency with cpu clock divide by 1 0.093 ?3.08 0 mhz maximum cpu frequency is 3 mhz at 2.7 v. with the cpu clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements f oscext frequency with cpu clock divide by 2 or greater 0.186 ? 6.35 mhz if the frequency of the external clock is greater than 3 mhz, the cpu clock divider must be set to 2 or greater. in this case, the cpu clock divider ensures that the fifty percent duty cycle requirement is met ? high period with cpu clock divide by 1 160 ? 5300 ns ? low period with cpu clock divide by 1 160 ? ?ns ? power-up imo to switch 150 ? ?s [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 31 of 47 ac programming specifications ta b l e 3 1 lists the guaranteed maximum and minimum specifications fo r the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, or 3.0 v to 3.6 v and ?40 c t a 85 c, respectively. typical parameters ar e measured at 5 v, 3.3 v, or 2.7 v at 25 c and are for design guidance only. ac i 2 c specifications the following tables list the guaranteed maximum and minimum spec ifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c t a 85 c, 3.0 v to 3.6 v and ?40 c t a 85 c, or 2.4 v to 3.0 v and ?40 c t a 85 c, respectively. typical parameters are measured at 5 v, 3.3 v, or 2.7 v at 25 c and are for design guidance only. table 31. ac programming specifications symbol description min typ max units notes t rsclk rise time of sclk 1 ? 20 ns t fsclk fall time of sclk 1 ? 20 ns t ssclk data setup time to falling edge of sclk 40 ? ? ns t hsclk data hold time from falling edge of sclk 40 ? ? ns f sclk frequency of sclk 0 ? 8 mhz t eraseb flash erase time (block) ? 10 ? ms t write flash block write time ? 40 ? ms t dsclk data out delay from falling edge of sclk ? ? 45 ns 3.6 < v dd t dsclk3 data out delay from falling edge of sclk ? ? 50 ns 3.0 v dd 3.6 t dsclk2 data out delay from falling edge of sclk ? ? 70 ns 2.4 v dd 3.0 t eraseall flash erase time (bulk) ? 20 ? ms erase all blocks and protection fields at once t program_hot flash block erase + flash block write time ? ? 100 [26] ms 0 c tj 100 c t program_cold flash block erase + flash block write time ? ? 200 [26] ms ?40 c tj 0 c table 32. ac characteristics of the i 2 c sda and scl pins for v dd 3.0 v symbol description standard mode fast mode units min max min max f scli2c scl clock frequency 0 100 0 400 khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated 4.0 ?0.6 ?s t lowi2c low period of the scl clock 4.7 ?1.3 ?s t highi2c high period of the scl clock 4.0 ?0.6 ?s t sustai2c setup time for a repeated start condition 4.7 ?0.6 ?s t hddati2c data hold time 0 ?0 ?s t sudati2c data setup time 250 ? 100 [27] ?ns t sustoi2c setup time for stop condition 4.0 ?0.6 ?s t bufi2c bus free time between a stop and start condition 4.7 ?1.3 ?s t spi2c pulse width of spikes suppressed by the input filter. ? ?050ns notes 26. for the full industrial range, the user mu st employ a temperature sensor user mo dule (flashtemp) and feed the result to the temperature argument before writing. refer to the flash apis application note an2015 (design aids - reading and writing psoc ? flash) for more information. 27. a fast-mode i 2 c-bus device may be used in a standard-mode i 2 c-bus system, but it must meet the requirement t su;dat 250 ns. this is automatically the case if the device does not stretch the low period of the scl signal. if the device does st retch the low period of the scl signal, it m ust output the next data bit to the sda line t rmax + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is released. [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 32 of 47 figure 14. definition for timing for fast/standard mode on the i 2 c bus table 33. 2.7-v ac characteristics of the i 2 c sda and scl pins (fast mode not supported) symbol description standard mode fast mode units min max min max f scli2c scl clock frequency 0 100 ??khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ? ? ?s t lowi2c low period of the scl clock 4.7 ? ? ?s t highi2c high period of the scl clock 4.0 ? ? ?s t sustai2c setup time for a repeated start condition 4.7 ? ? ?s t hddati2c data hold time 0 ? ? ?s t sudati2c data setup time 250 ? ? ?ns t sustoi2c setup time for stop condition 4.0 ? ? ?s t bufi2c bus free time between a stop and start condition 4.7 ?? ?s t spi2c pulse width of spikes are suppressed by the input filter. ? ???ns i2c_sda i2c_scl s sr s p t bufi2c t spi2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c start condition repeated start condition stop condition [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 33 of 47 packaging information this section shows the packaging specific ations for the cy8c21x34b psoc device with the thermal impedances for each package. important note emulation tools may require a larger area on the target pcb than the chip's footprint. fo r a detailed description of the emulation tools' dimensions, refe r to the emulator pod drawings at http://www.cypress.com. figure 15. 16-pin (150-mil) soic figure 16. 20-pin (210-mil) ssop 51-85068 *c 51-85077 *e [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 34 of 47 figure 17. 28-pin (210-mil) ssop figure 18. 32-pin qfn ( 5 x 5 x 1.0 mm) lt32b (3.5 x 3.5) epad (sawn) 51-85079 *e 001-30999 *c [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 35 of 47 figure 19. 32-pin (5 5 0.4 mm) qfn (sawn 1.85 2.85) epad figure 20. 32-pin thin sawn qfn package important note for information on the preferred dimensio ns for mounting qfn packages, see the application notes for surface mount assembly of amkor's microleadframe (mlf) packages available at http://www.amkor.com . 3. reference jedec #: mo-220 2. all dimensions are in millimeters. notes : 1. hatch area is solderable exposed pad. top view 9 8 1 32 16 17 24 25 pin 1 i.d 4. maximum allowable metal is 0.0508mm 0.4000.100 0.15max pin#1 (laser marked) 5. package weight: 0.029 grams 0.064 -0.090 bare cooper 0.127 0.064 1.850.10 solderable exposed pad 2.850.10 0.400 0.10 min bottom view 0.500 0.250.040 0.300 min [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 36 of 47 figure 21. 56-pin (300-mil) ssop thermal impedances solder reflow peak temperature ta b l e 3 5 lists the maximum solder reflow peak temperatures to ac hieve good solderability. thermal ramp rate during preheat should be 3 c/s or lower. 51-85062 *d table 34. thermal impedances per package package typical ja [28] typical jc 16-pin soic 123 c/w 55 c/w 20-pin ssop 117 c/w 41 c/w 28-pin ssop 96 c/w 39 c/w 32-pin qfn [29] 5 5 mm 0.60 max 27 c/w 15 c/w 32-pin qfn [29] 5 5 mm 0.93 max 22 c/w 12 c/w 56-pin ssop 48 c/w 24 c/w table 35. solder reflow peak temperature package maximum peak temperature time at maximum temperature 16-pin soic 260 c 20 s 20-pin ssop 260 c 20 s 28-pin ssop 260 c 20 s 32-pin qfn 260 c 20 s 56-pin ssop 260 c 20 s notes 28. t j = t a + power ja 29. to achieve the thermal impedance spec ified for the qfn package, refer to application notes for surface mount assembly of amkor's microleadframe (mlf) packages available at http://www.amkor.com . 30. higher temperatures may be required based on the solder me lting point. typical temperatures for solder are 220 5 c with sn-pb or 245 5 c with sn-ag-cu paste. refer to the solder manufacturer specifications. [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 37 of 47 development tool selection this section presents the development tools available for all current psoc device families including the cy8c21x34b family. software psoc designer ? at the core of the psoc development software suite is psoc designer, used to generate psoc firmware applications. psoc designer is available free of charge at http://www.cypress.com and includes a free c compiler. psoc programmer flexible enough to be used on the bench in development, yet suitable for factory programming, psoc programmer works either as a standalone programmi ng application or operates directly from psoc designer. psoc programmer software is compatible with both psoc ice-cube in-circuit emulator and psoc miniprog. psoc programmer is available free of charge at http://www.cypress.com. development kits all development kits can be purchased from the cypress online store. cy3215-dk basic development kit the cy3215-dk is for prototyping and development with psoc designer. this kit supports in-circuit emulation, and the software interface allows you to run, halt, and single step the processor, and view the content of specific memo ry locations. advance emulation features also supported through psoc designer. the kit includes: psoc designer software cd ice-cube in-circuit emulator ice flex-pod for cy8c29x66 family cat-5 adapter mini-eval programming board 110 ~ 240 v power supply, euro-plug adapter imagecraft c compiler issp cable usb 2.0 cable and blue cat-5 cable two cy8c29466-24pxi 28-pdip chip samples evaluation tools all evaluation tools can be purchased from the cypress online store. cy3210-miniprog1 the cy3210-miniprog1 kit allows you to program psoc devices through the miniprog1 programming unit. the miniprog is a small, compact prototyping programmer that connects to the pc through a provided usb 2.0 cable. the kit includes: miniprog programming unit minieval socket programming and evaluation board 28-pin cy8c29466-24pxi pdip psoc device sample 28-pin cy8c27443-24pxi pdip psoc device sample psoc designer software cd getting started guide usb 2.0 cable cy3210-psoceval1 the cy3210-psoceval1 kit features an evaluation board and the miniprog1 programming unit. the evaluation board includes an lcd module, potentiometer, leds, and plenty of bread- boarding space to meet all of your evaluation needs. the kit includes: evaluation board with lcd module miniprog programming unit two 28-pin cy8c29466-24pxi pdip psoc device samples psoc designer software cd getting started guide usb 2.0 cable cy3214-psocevalusb the cy3214-psocevalusb evaluation kit features a development board for the cy8c24794-24lfxi psoc device. the board includes both usb and capacitive sensing development and debugging support. this evaluation board also includes an lcd module, potentiometer, leds, an enunciator and plenty of breadboarding space to meet all of your evaluation needs. the kit includes: psocevalusb board lcd module miniprog programming unit mini usb cable psoc designer and example projects cd getting started guide wire pack [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 38 of 47 device programmers all device programmers can be purchased from the cypress online store. cy3216 modular programmer the cy3216 modular programmer kit features a modular programmer and the miniprog1 programming unit. the modular programmer includes three programming module cards and supports multiple cypress products. the kit includes: modular programmer base three programming module cards miniprog programming unit psoc designer software cd getting started guide usb 2.0 cable cy3207issp in-system serial programmer (issp) the cy3207issp is a production programmer. it includes protection circuitry and an industria l case that is more robust than the miniprog in a production-programming environment. note cy3207issp needs special software and is not compatible with psoc programmer. the kit includes: cy3207 programmer unit psoc issp software cd 110 ~ 240 v power supply, euro-plug adapter usb 2.0 cable accessories (emulation and programming) table 36. emulation and programming accessories part number pin package flex-pod kit [31] foot kit [32] adapter CY8C21234B-24sxi 16-pin soic cy3250-21x34 c y3250-16soic-fk adapters can be found at http://www.emulation.com . cy8c21334b-24pvxi 20-pin ssop cy3250-21x34 cy3250-20ssop-fk cy8c21534b-24pvxi 28-pin ssop cy3250-21x34 cy3250-28ssop-fk notes 31. flex-pod kit includes a practice flex-pod and a practice pcb, in addition to two flex-pods. 32. foot kit includes surface mount feet that can be so ldered to the target pcb. [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 39 of 47 ordering information note for die sales information, contact a local cypress sales office or field applications engineer (fae). package ordering code flash (bytes) sram (bytes) switch mode pump temperature range digital blocks analog blocks digital i/o pins analog inputs analog outputs xres pin 16-pin (150-mil) soic cy8c21x34b-24sxi 8 k 512 yes ?40 c to +85 c 4 4 12 12 [33] 0 no 16-pin (150-mil) soic (tape and reel) cy8c21x34b-24sxit 8 k 512 yes ?40 c to +85 c 4 4 12 12 [33] 0 no 20-pin (210-mil) ssop cy8c21x34b-24pvxi 8 k 512 no ?40 c to +85 c 4 4 16 16 [33] 0 yes 20-pin (210-mil) ssop (tape and reel) cy8c21x34b-24pvxit 8 k 512 no ?40 c to +85 c 4 4 16 16 [33] 0 yes 28-pin (210-mil) ssop cy8c21x34b-24pvxi 8 k 512 no ?40 c to +85 c 4 4 24 24 [33] 0 yes 28-pin (210-mil) ssop (tape and reel) cy8c21x34b-24pvxit 8 k 512 no ?40 c to +85 c 4 4 24 24 [33] 0 yes 32-pin (5 5 mm 1.00 max) sawn qfn cy8c21x34b-24ltxi 8 k 512 no ?40 c to +85 c 4 4 28 28 [33] 0 yes 32-pin (5 5 mm 1.00 max) sawn qfn [34] (tape and reel) cy8c21x34b-24ltxit 8 k 512 no ?40 c to +85 c 4 4 28 28 [33] 0 yes 32-pin (5 5 mm 0.40 max) sawn qfn [34] cy8c21x34b-24lcxi 8 k 512 no ?40 c to +85 c 4 4 28 28 [33] 0 yes 32-pin (5 5 mm 0.40 max) sawn qfn [34] (tape and reel) cy8c21x34b-24lcxit 8 k 512 no ?40 c to +85 c 4 4 28 28 [33] 0 yes 32-pin (5 5 mm 0.60 max) thin sawn qfn cy8c21x34b-24lqxi 8 k 512 no ?40 c to +85 c 4 4 28 28 [33] 0 yes 32-pin (5 5 mm 0.60 max) thin sawn qfn (tape and reel) cy8c21x34b-24lqxit 8 k 512 no ?40 c to +85 c 4 4 28 28 [33] 0 yes 56-pin ocd ssop cy8c21001-24pvxi 8 k 512 yes ?40 c to +85 c 4 4 26 26 [33] 0 yes notes 33. all digital i/o pins also connect to the common analog mux. 34. refer to the section 32-pin part pinout on page 11 for pin differences. [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 40 of 47 ordering code definitions cy marketing code: 8 = cypress psoc 8 c family code technology code: c = cmos company id: cy = cypress 21 part number speed: 24 mhz xx xxxx-24 package type: thermal rating: px = pdip pb-free c = commercial sx = soic pb-free i = industrial pvx = ssop pb-free e = extended lfx/lkx/ltx/lcx/lqx = qfn pb-free [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 41 of 47 acronyms ta b l e 3 7 lists the acronyms that are used in this document. reference documents cy8cplc20, cy8cled16p01, cy8c29x66, cy8c27x43, cy8c24 x94, cy8c24x23, cy8c24x23a, cy8c22x13, cy8c21x34b, cy8c21x23, cy7c64215, cy7c603xx, cy8cnp1xx, and cywusb6953 psoc ? programmable system-on-chip technical reference manual (trm) (001-14463) design aids ? reading and writing psoc ? flash - an2015 (001-40459) adjusting psoc ? trims for 3.3 v and 2.7 v operation ? an2012 (001-17397) understanding datasheet jitter specifications for cypress timing products ? an5054 (001-14503) application notes for surface mount assembly of amkor's microleadframe (mlf) packages ? available at http://www.amkor.com . table 37. acronyms used in this datasheet acronym description acronym description ac alternating current mips million instructions per second adc analog-to-digital converter ocd on-chip debug api application programming interface pcb printed circuit board cmos complementary metal oxide semicon ductor pdip plastic dual-in-line package cpu central processing unit pga programmable gain amplifier crc cyclic redundancy check pll phase-locked loop ct continuous time por power on reset dac digital-to-analog converter ppor precision power on reset dc direct current prs pseudo-random sequence dtmf dual-tone multi-frequency psoc ? programmable system-on-chip eco external crystal oscillator pwm pulse width modulator eeprom electrically erasable programmable read-only memory qfn quad flat no leads gpio general purpose i/o rtc real time clock ice in-circuit emulator sar successive approximation ide integrated development environment sc switched capacitor ilo internal low speed oscillator slimo slow imo imo internal main oscillator smp switch-mode pump i/o input/output soic small-ou tline integrated circuit irda infrared data association spi tm serial peripheral interface issp in-system serial programming sram static random access memory lcd liquid crystal display srom supervisory read only memory led light-emitting diode ssop shrink small-outline package lpc low power comparator uart universal asynchronous receiver / transmitter lvd low voltage detect usb universal serial bus mac multiply-accumulate wdt watchdog timer mcu microcontroller uni t xres external reset [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 42 of 47 document conventions units of measure ta b l e 3 8 lists the units of measures. numeric conventions hexadecimal numbers are represented with all letters in uppercase wi th an appended lowercase ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? pref ix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, 01010100b? or ?01000011b?). numbers not indicated by an ?h? or ?b? are decimals. table 38. units of measure symbol unit of measure symbol unit of measure kb 1024 bytes h microhenry db decibels s microsecond c degree celsius ms millisecond f microfarad ns nanosecond ff femto farad ps picosecond pf picofarad v microvolts khz kilohertz mv millivolts mhz megahertz mvpp millivolts peak-to-peak rt-hz root hertz nv nanovolts k kilohm v volts ohm w microwatts a microampere w watt ma milliampere mm millimeter na nanoampere ppm parts per million pa pikoampere % percent mh millihenry glossary active high 1. a logic signal having its asserted state as the logic 1 state. 2. a logic signal having the logic 1 state as the higher voltage of the two states. analog blocks the basic programmable opamp circuits. these are sc (switched capacitor) and ct (continuous time) blocks. these blocks can be interconnected to provide adcs, dacs, mu lti-pole filters, gain stages, and much more. analog-to-digital (adc) a device that changes an analog signal to a digital signal of corresponding magnitude. typically, an adc converts a voltage to a digital number. the digital-to-analog (dac) converter performs the reverse operation. application programming interface (api) a series of software routines that comprise an interface between a computer application and lower level services and functions (for exampl e, user modules and libraries). apis serve as building blocks for programmers that create softwa re applications. asynchronous a signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal. bandgap reference a stable voltage reference design that matches the positive temperature coefficient of vt with the negative temperat ure coefficient of vbe, to produce a ze ro temperature coefficient (ideally) reference. [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 43 of 47 bandwidth 1. the frequency range of a message or information processing system measured in hertz. 2. the width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is sometimes represented more specific ally as, for example, full width at half maximum. bias 1. a systematic deviation of a value from a reference value. 2. the amount by which the average of a set of values departs from a reference value. 3. the electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device. block 1. a functional unit that performs a single function, such as an oscillator. 2. a functional unit that may be configured to perfo rm one of several functions, such as a digital psoc block or an analog psoc block. buffer 1. a storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. usually refers to an area reserved for io operations, into which data is read, or from which data is written. 2. a portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3. an amplifier used to lower the output impedance of a system. bus 1. a named connection of nets. bundling nets together in a bus makes it easier to route nets with similar routing patterns. 2. a set of signals performing a common function and carrying similar data. typically represented using vector notation; fo r example, address[7:0]. 3. one or more conductors that serve as a co mmon connection for a group of related devices. clock the device that generates a periodic signal with a fixed frequen cy and duty cycle. a clock is sometimes used to synchroni ze different logic blocks. comparator an electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. compiler a program that translates a high leve l language, such as c, into machine language. configuration space in psoc devices, the register space accessed when the xio bit, in the cpu_f register, is set to ?1?. crystal oscillator an oscillator in whic h the frequency is controlled by a piezoelectric crystal. typically a piezoelectric crystal is less sensitive to ambient te mperature than other circuit components. cyclic redundancy check (crc) a calculation used to detect errors in data co mmunications, typically performed using a linear feedback shift register. similar calculations may be used for a variety of other purposes such as data compression. data bus a bi-directional set of signals used by a comp uter to convey information from a memory location to the central processing unit and vice versa. more generally, a set of signals used to convey data between digital functions. debugger a hardware and software system that allo ws you to analyze the operation of the system under development. a debugger usually allows th e developer to step through the firmware one step at a time, set break points, and analyze memory. dead band a period of time when neither of two or more signals are in their active state or in transition. glossary (continued) [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 44 of 47 digital blocks the 8-bit logic blocks that can act as a counter, timer, se rial receiver, serial transmitter, crc generator, pseudo-random number generator, or spi. digital-to-analog (dac) a device that changes a digital signal to an analog signal of corresponding magnitude. the analog- to-digital (adc) converter pe rforms the reverse operation. duty cycle the relations hip of a clock period high time to its low time, expressed as a percent. emulator duplicates (provides an emul ation of) the functions of one system with a different system, so that the second system appears to behave like the first system. external reset (xres) an active high signal that is driven into the psoc device. it causes all operation of the cpu and blocks to stop and return to a pre-defined state. flash an electrically programmable and erasable, non-volatile technology that provides you the programmability and data storage of eproms, pl us in-system erasability. non-volatile means that the data is retained when power is off. flash block the smallest amount of flash rom space that may be programmed at one time and the smallest amount of flash space that may be pr otected. a flash block holds 64 bytes. frequency the number of cycles or events pe r unit of time, for a periodic function. gain the ratio of output current, vo ltage, or power to input current, voltage, or power, respectively. gain is usually expressed in db. i 2 c a two-wire serial computer bus by philips semiconductors (now nxp semiconductors). i2c is an inter-integrated circuit. it is used to connect low-speed peripherals in an embedded system. the original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building control el ectronics. i2c uses only two bi-d irectional pins, clock and data, both running at +5v and pulle d high with resistors. the bus operates at 100 kbits/second in standard mode an d 400 kbits/second in fast mode. ice the in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging device activity in a software environment (psoc designer). input/output (i/o) a device that introduces da ta into or extracts data from a system. interrupt a suspension of a process, such as the ex ecution of a computer program, caused by an event external to that process, and performed in such a way that the process can be resumed. interrupt service routine (isr) a block of code that normal code execution is diverted to when the m8c receives a hardware interrupt. many interrupt sources may each exis t with its own priority and individual isr code block. each isr code block ends with the reti in struction, returning t he device to the point in the program where it left normal program execution. jitter 1. a misplacement of the timing of a transition from its ideal position. a ty pical form of corruption that occurs on serial data streams. 2. the abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequen cy or phase of successive cycles. low-voltage detect (lvd) a circuit that senses vdd and provides an interrupt to the system when vdd falls below a selected threshold. glossary (continued) [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 45 of 47 m8c an 8-bit harvard-architecture microprocessor. the microprocessor coordinates all activity inside a psoc by interfacing to the fl ash, sram, and register space. master device a device that controls the timing for da ta exchanges between two devices. or when devices are cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external in terface. the controlled device is called the slave device . microcontroller an integrated circuit chip that is desi gned primarily for control systems and products. in addition to a cpu, a microcontroller typically includes memory, timing circuits, and io circuitry. the reason for this is to permit the realization of a co ntroller with a minimal quantity of chips, thus achieving maximal possible miniaturization. this in turn, reduces the volume and the cost of the controller. the microcontroller is normally not used for general-purpose computation as is a microprocessor. mixed-signal the reference to a circuit containing both analog and digital techniques and components. modulator a device that imposes a signal on a carrier. noise 1. a disturbance that affects a signal and that may distort the information carried by the signal. 2. the random variations of one or mo re characteristics of any entity such as voltage, current, or data. oscillator a circuit that may be crystal controlled and is used to generate a clock frequency. parity a technique for testing transmitting data. typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). phase-locked loop (pll) an electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal. pinouts the pin number assignment: the relation bet ween the logical inputs and outputs of the psoc device and their physical counterparts in t he printed circuit board (pcb) package. pinouts involve pin numbers as a link between schematic and pcb design (both being computer generated files) and may also involve pin names. port a group of pins, usually eight. power on reset (por) a circuit that forces the psoc device to reset when the voltage is below a pre-set level. this is one type of hardware reset. psoc ? cypress semiconductor?s psoc ? is a registered trademark and programmable system-on- chip? is a trademark of cypress. psoc designer? the software for cypress? programmable system-on-chip technology. pulse width modulator (pwm) an output in the form of duty cycle which varies as a function of the applied measurement ram an acronym for random access memory. a data-storage device from which data can be read out and new data can be written in. register a storage device with a specific capacity, such as a bit or byte. reset a means of bringing a system back to a know state. see hardware reset and software reset. glossary (continued) [+] feedback
cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B document number: 001-67345 rev. *a page 46 of 47 rom an acronym for read only memory. a data-storage device from which data can be read out, but new data cannot be written in. serial 1. pertaining to a process in which all events occur one after the other. 2. pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. settling time the time it takes for an output signal or value to stabilize after the input has changed from one value to another. shift register a memory storage device t hat sequentially shifts a word either left or right to output a stream of serial data. slave device a device that allows another device to control the timing for data exchanges between two devices. or when devices are cascaded in width, th e slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface. the controlling device is called the master device. sram an acronym for static random access memory. a memory device where you can store and retrieve data at a high rate of speed. the term static is used because, after a value is loaded into an sram cell, it remains unchanged until it is explicitly al tered or until power is removed from the device. srom an acronym for supervisory read only memory. the srom holds code that is used to boot the device, calibrate circuitry, and perform flash operations. the functions of the srom may be accessed in normal user code, operating from flash. stop bit a signal following a character or block that prepares the receiving device to receive the next character or block. synchronous 1. a signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. 2. a system whose operation is syn chronized by a clock signal. tri-state a function whose output ca n adopt three states: 0, 1, and z (high-impedance). the function does not drive any value in the z state and, in many respects, may be considered to be disconnected from the rest of the circuit, allowin g another output to drive the same net. uart a uart or universal asynchronous receiver-tra nsmitter translates between parallel bits of data and serial bits. user modules pre-build, pre-tested hardw are/firmware peripheral functions that take care of managing and configuring the lower level analog and digital psoc blocks. user modules also provide high level api (application programming interface) for the peripheral function. user space the bank 0 space of the register map. the re gisters in this bank are more likely to be modified during normal program execution and not just durin g initialization. registers in bank 1 are most likely to be modified only during the initialization phase of the program. v dd a name for a power net meaning ?voltage drain?. the most positive power supply signal. usually 5 v or 3.3 v. v ss a name for a power net meaning ?voltage source ?. the most negative power supply signal. watchdog timer a timer that must be serviced periodically. if it is not serviced, the cpu resets after a specified period of time. glossary (continued) [+] feedback
document number: 001-67345 rev. *a revised may 13, 2011 page 47 of 47 psoc designer? and programmable system-on-chip? are trademarks and psoc ? and capsense ? are registered trademarks of cypress semiconductor corporation. purchase of i 2 c components from cypress or one of its sublicensed a ssociated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. as from october 1st, 2006 philips semiconductors has a new trade name - nxp sem iconductors. all products and company names mentioned in this document may be the trademarks of their respective holders. cy8c21634b, cy8c 21534b, cy8c21434b cy8c21334b, CY8C21234B ? cypress semiconductor corporation, 2011. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rig hts. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypres s. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a ma lfunction or failure may reasonably be expe cted to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 document history page document title: CY8C21234B, cy8c21334b, cy8c21434b, cy8c21534b, cy8c21634b psoc ? programmable system-on-chip? document number: 001-67345 revision ecn orig. of change submission date description of change ** 3169205 yva 02/16/2011 new datasheet *a 3247292 yva 05/11/2011 updated package diagrams. post to web. [+] feedback

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